ESD protection for passive integrated devices

ABSTRACT

Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional of Ser. No. 11/300,710 filed on Dec.14, 2005.

The present invention generally relates to protection of electronicdevices against damage from electrostatic discharge (ESD), and moreparticularly relates to ESD protection of integrated passive devices.

BACKGROUND

Modern electronic devices are susceptible to damage from transientelectrostatic discharge, commonly referred to as “ESD.” ESD events oftenoccur when a person whose body has accumulated a static charge, touchesor handles the electronic device. Static charge build-up can occur froma person walking across a carpeted surface or as a result of motion ofcertain types of clothing or from other sources. In any case, when theelectronic device is touched by a charged person or other object, thebuilt-up charge can be suddenly discharged through the electronicdevice. This can result in catastrophic damage to the electronic device.Accordingly, many electronic devices include some type of internal ESDprotection. This often takes the form of an auxiliary transistor orZener diode or other non-linear semiconductor device placed between oneor more of the input/output (I/O) terminals of the electronic elementbeing protected and a reference potential or common connection. Thisprotective device detects the sudden rise in terminal voltage producedby the ESD event and switches on or otherwise creates a relatively lowimpedance path to the reference connection, thereby shunting the ESDcurrent harmlessly to ground. Such ESD protection arrangements take manyforms well known in the art. They have in common the above-noted featurethat they normally present comparatively high impedance to the circuitthey are protecting so as not interfere with its normal operation butare triggered into activity by the rising ESD pulse. As the leading edgeof the ESD pulse is sensed, they switch to a low impedance state therebylimiting the voltage rise produced by the ESD pulse, in effect, clippingthe top off the ESD pulse. When the ESD transient has passed, theyonce-again revert to a high impedance state. While such prior atarrangements work well in connection with active devices and integratedcircuits, they are generally not applicable to integrated passivecomponents where the necessary non-linear semiconductor devices or othertype of non-linear spark-arrestors are not available. Accordingly therecontinues to be a need for means and method for protecting integratedpassive devices. As used herein, the word “integrated” is intended toinclude elements formed in or on a common substrate. Thin filmconductors and dielectrics are commonly used in integrated passivedevices.

Accordingly, it is desirable to provide an improved means and method forESD protection of electronic devices, especially for integrated passivedevices. In addition, it is desirable that the means and method forproviding such protection be generally compatible with availablefabrication methods for such electronic devices so as to not requiresubstantial changes in the manufacturing process. Furthermore, otherdesirable features and characteristics of the present invention willbecome apparent from the subsequent detailed description and theappended claims, taken in conjunction with the accompanying drawings andthe foregoing technical field and background.

BRIEF SUMMARY

Methods are provided for an electrostatic discharge (ESD) protectedelectronic apparatus. In one embodiment, the method includes the stepsof: (i) providing a substrate; (ii) forming a dielectric layer over thesubstrate; (iii) forming a conductive layer over the dielectric layer;(iv) forming a first down-lead extending from the conductive layer,through the dielectric layer, and to the substrate; (v) forming a seconddown-lead extending from the conductive layer, through the dielectriclayer, and to the substrate, the second down-lead laterally spaced apartfrom the first down-lead; and (vi) forming at least one passive elementelectrically coupled to the first down-lead. The first down-lead, thesecond down-lead, and the substrate are formed such that a chargeleakage resistance path is created between the first-down lead and thesecond down-lead through the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will hereinafter be described in conjunction withthe following drawing figures, wherein like numerals denote likeelements, and

FIG. 1 is a simplified schematic circuit of an integrated passivecoupler, according to the prior art;

FIG. 2 is a simplified schematic circuit of an integrated passivecoupler, according an embodiment of the present invention;

FIG. 3 is a simplified schematic circuit of an integrated passivecapacitor, according to the prior art;

FIG. 4 is a simplified schematic circuit of an integrated passivecapacitor, according a further embodiment of the present invention;

FIG. 5 is a simplified plan view of an integrated passive device (IPD)RF coupler according to another embodiment of the present invention;

FIG. 6 is a simplified partial cross-sectional view through the IPD RFcoupler of FIG. 5;

FIGS. 7-16 are sequential cross-sectional views illustrating a method offabrication of an integrated passive device according to a still furtherembodiment of the present invention;

FIGS. 17-24 are sequential partial cross-sectional views illustratingsteps in a method of fabrication of an integrated passive deviceaccording to a yet further embodiment of the present invention; and

FIG. 25 is a plan view of a portion of the integrated passive deviceillustrated in FIG. 23.

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and isnot intended to limit the invention or the application and uses of theinvention. Furthermore, there is no intention to be bound by anyexpressed or implied theory presented in the preceding technical field,background, brief summary or the following detailed description.

For simplicity and clarity of illustration, the drawing figuresillustrate the general manner of construction, and descriptions anddetails of well-known features and techniques may be omitted to avoidunnecessarily obscuring the invention. Additionally, elements in thedrawings figures are not necessarily drawn to scale. For example, thedimensions of some of the elements or regions in the figures may beexaggerated relative to other elements or regions to help improveunderstanding of embodiments of the invention.

The terms “first,” “second,” “third,” “fourth” and the like in thedescription and the claims, if any, may be used for distinguishingbetween similar elements and not necessarily for describing a particularsequential or chronological order. It is to be understood that the termsso used are interchangeable under appropriate circumstances such thatthe embodiments of the invention described herein are, for example,capable of operation in sequences other than those illustrated orotherwise described herein. Furthermore, the terms “comprise,”“include,” “have” and any variations thereof, are intended to covernon-exclusive inclusions, such that a process, method, article, orapparatus that comprises a list of elements is not necessarily limitedto those elements, but may include other elements not expressly listedor inherent to such process, method, article, or apparatus.

The terms “left,” right,” “in,” “out,” “front,” “back,” “up,” “down,“top,” “bottom,” “over,” “under,” “above,” “below” and the like in thedescription and the claims, if any, are used for descriptive purposesand not necessarily for describing permanent relative positions. It isto be understood that the terms so used are interchangeable underappropriate circumstances such that embodiments of the inventiondescribed herein are, for example, capable of operation in otherorientations than those illustrated or otherwise described herein. Theterm “coupled,” as used herein, is defined as directly or indirectlyconnected in an electrical or non-electrical manner.

FIG. 1 is a simplified schematic circuit of integrated passive coupler(IPC) 40, according to the prior art. Integrated passive coupler 40comprises magnetically coupled coils 42, 43 having terminals 4201, 4202and 4301, 4302 respectively, all mounted on substrate 41. IPC 40 isgenerally formed using thin films that are deposited by various methodswell known in the art on substrate 41. When formed by thin filmtechnology, coils 42, 43 generally have a spiral shape in plan view butother shapes are not precluded. Substrate 41 is conveniently aninsulating or semi-insulating substrate. The distance between coils 42,43 is exaggerated in FIGS. 1-2 to facilitate better understanding.

FIG. 2 is a simplified schematic circuit of integrated passive coupler(IPC) 44, according to an embodiment of the present invention. Likereference numbers are used to identify like elements in FIGS. 1 and 2.Integrated passive coupler 44 comprises magnetically coupled coils 42,43 having terminals 4201, 4202 and 4301, 4302 respectively, all mountedon substrate 41. IPC 44 is generally formed using thin films that aredeposited by various methods well known in the art on substrate 41.Coils 42, 43 can be substantially the same as those in IPC 40 except forthe extra connections provided by the embodiment of the presentinvention. It has been found that the ESD tolerance of passive elementssuch as coupler 44 can be substantially improved without adverselyaffecting the ordinary performance of coupler 44 by providing one ormore high resistance leakage paths 45 electrically coupling the windingsof coils 42, 43. Advantage is taken of the fact that substrate 41 is asemi-insulating material, that is, generally having a resistivityusefully greater than about 1E3 ohms-cm, conveniently between 1E3 and1E10 ohms-cm. and preferably between 1E7 and 1E9 ohms-cm. Un-doped GaAsor other III-V compounds are examples of suitable semi-insulatingmaterials useful for substrate 41, but this is merely by way of exampleand not intended to be limiting. A wide variety of other materials wellknown in the art can also be used.

High resistance leakage paths are desirably created by coupling variouswindings of coils 42, 43 to substrate 41 via spaced-apart leads orconductors 46. Thus, conductors 461, 462, 463 couple portions 421, 422,423 respectively of coil 42 to locations 471, 472, 473 on substrate 41and conductors 464, 465, 466 couple portions 431, 432, 433 respectivelyof coil 43 to locations 474, 475, 476 on substrate 41. Locations 471,472, 473 and locations 474, 475, 476 are spaced apart, for example, bydistance 49 (individual distances may be varied) so that resistances451, 452, 453 respectively (collectively 45) are formed between suchconnections. Depending upon the resistivity of substrate 41, distances49 are chosen so that the resulting resistances 45 are usefully of theorder of at least about 1E6 Ohms, conveniently at least about 1E8 Ohmsand preferably about 1E9 Ohms. Larger or smaller values can be also beused. What is important is that resistances 45 be sufficiently high soas to not significantly degrade the performance of coupler 44 at thefrequencies of interest and sufficiently low so as to inhibit thebuild-up of static charge between coils 42, 43. It has been found thatresistances 45 in the range of about 1E6 to 1E11 Ohms are useful, withresistance of about 1E8 to 1E11 Ohms being convenient and resistances ofabout 1E8 to 5E10 Ohms being preferred. Stated another way, resistances45 are usefully in the range of at least 100 times the operatingimpedance of coupler 44 at the frequencies of interest, conveniently atleast a 500 times the operating impedance of coupler 44 at thefrequencies of interest and preferably at least 1000 times the operatingimpedance of coupler 44 at the frequencies of interest. However, largeror smaller ratios can also be used depending upon the performancerequirements of coupler 44. While coils 42, 43 are shown in FIG. 2 asbeing coupled via three resistances 451, 452, 453 connected to differentlocations on coils 42, 43, this is merely by way of example and notintended to be limiting. The present invention only requires that therebe at least one relatively high value resistance coupling those portionsof passive element 40 across which an ESD voltage can appear. Dependingupon the physical size of the element being protected and its operatingimpedance, multiple spaced-apart high resistance paths can be providedor a distributed high resistance path can be provided. Eitherarrangement is useful. Persons of skill in the art will understand basedon the description herein how to choose the most effective locations andsize of the high resistance paths useful for improving the ESDperformance of their particular IPD.

FIG. 3 is a simplified schematic circuit of integrated passive coupler50 according to the prior art, comprising capacitor 52 with terminals5201, 5202, formed on insulating or semi-insulating substrate 51. IPC 50is conveniently formed using thin film techniques. For example, thinmetal films separated by a deposited dielectric are used to formcapacitor 52 and its associated terminals.

FIG. 4 is a simplified schematic circuit of integrated passive coupler(IPC) 54 analogous to coupler 50, but according a further embodiment ofthe present invention. Coupler 54 comprises capacitor 52 with terminals5201, 5202 disposed on substrate 51 analogous to substrate 41 of FIG. 2.Advantage is taken of semi-insulating substrate 51 by providingconductors 56 coupling terminals 521, 523 on opposite sides of capacitor52 to spaced-apart locations 522, 524 respectively on substrate 51.Locations 522, 524 are spaced apart by distance 57, providingcomparatively high value resistance 55 therebetween. Resistance 55should be sufficiently high so as to not interfere with the normaloperation of capacitor 52 at the frequencies of interest and still lowenough to provide improved bleed off of excessive charge, therebyimproving the ESD performance of IPC 54. The same considerations applyin choosing the resistivity of substrate 51 and distance 57 as describedin connection with IPC 44 of FIG. 2 and the discussion thereof isincorporated herein by reference. Substantially the same ranges ofresistivity and resistance apply.

FIG. 5 is a simplified plan view and FIG. 6 is a partial cross-sectionalview of integrated passive device (IPD) RF coupler 60 according toanother embodiment of the present invention. Integrated passive coupler(IPC) 60 comprises insulating or semi-insulating substrate 61 analogousto substrates 41, 51 of FIGS. 2 and 4 on which are formed, e.g., by thinor thick film techniques, serially coupled first connection terminal orbonding pad 62, capacitor 63, inductor 64 and second connection terminalor bonding pad 65. Persons of skill in the art will understand based onthe description herein that the choice and arrangement of elements 62-65is merely by way of example and not intended to be limiting and that anynumber of passive (and/or active) elements could be included onsubstrate 61, coupled in various series-parallel combinations. Thepresent invention is applicable to such further arrangements and is notlimited merely to the particular examples shown herein, which areprovided merely for convenience of description and not by way oflimitation. Referring now to FIGS. 5 and 6 together, first dielectriclayer 671 overlies upper surface 611 of substrate 61. First metal layer68, supported by first dielectric layer 671, is conveniently used toform first bonding terminal 62 and lower plate 631 of capacitor 63 andto form second bonding terminal 65 including portion 651 extendingunderneath central portion 641 of inductor 64, to make electricalconnection thereto. Second dielectric layer 672 is provided overportions of first dielectric layer 671 and first metal layer 68. Seconddielectric layer 672 provides dielectric 633 in capacitor 63 andsupports second metal layer 69 comprising upper plate 632 of capacitor63 and spiral shaped inductor 64. A portion of metal layer 69 atlocation 641 in the center of inductor 64 conveniently (but notessentially) makes contact to portion 651 of first metal layer 68 so asto couple inductor 64 to terminal connection pad 65. This arrangement isby way of example and not intended to be limiting. As will be understoodby persons of skill in the art, elements 63-65 can be coupled in anynumber of ways using either of metal layers 68, 69 or further metallayers. Leads 701-706 (collectively 70) are provided extending betweenmetal layers 68, 69 and spaced-apart locations 711-716 on substrate 61.Leads 701, 702, 706 extend from first metal layer 68 to substrate 61 andLeads 703, 704, 705 extend from second metal layer 69 to substrate 61.When substrate 61 is a semi-insulating material, analogous to substrates41, 51 of FIGS. 2 and 4, then resistances 751-755 tying together thevarious metal regions of elements 62-65 are created by the combinationof leads 70 and substrate 61. When substrate 61 is semi-insulating asdiscussed in connection with FIGS. 2 and 4, then resistance 751-755 canbe arranged to have the appropriate values by adjusting their number andspacing and the resistivity of substrate 61. In that situation, thenleads 70 should be comparatively conductive that is, generally 1E3 to1E10 times more conductive than substrate 61 since they are not beingrelied on to provide the high value resistance for charge bleed off, butthis is not essential.

The present invention works even when substrate 61 is insulating or ofrelatively high conductivity, that is, not a semi-insulating material.When substrate 61 is an insulating material and cannot be relied on toprovide the charge bleed-off resistance, then a high resistivity film isdeposited on surface 611 of substrate 61 (e.g., see FIGS. 17-25)underneath first dielectric layer 671, and leads 701, . . . , 706 makecontact to such high resistivity film, which then provides resistances751-755. If substrate 61 is too highly conductive to provide the desiredhigh value resistances 751-755, then the roles of down-leads 701-706 andsubstrate 61 can reversed. That is, leads 701-706 can be formed fromhigh resistivity material leading to comparatively conductive substrate61, thereby provided the high resistance values desired so as to notcompromise the ordinary operation of coupler 60 at the frequency rangesof interest. Un-doped or lightly doped semiconductors are suitablematerials for leads 701-706 with this configuration, i.e., with highresistance down-leads going to a comparatively conductive substrate.Alternatively, the surface of substrate 61 can be converted or coatedwith an insulating layer and the high resistivity film formed thereon.Either approach is useful.

FIGS. 7-16 are sequential partial cross-sectional views 401-410illustrating a method of fabrication of an integrated passive device,analogous to device 60 of FIG. 6, according to a still furtherembodiment of the present invention. In FIGS. 7-16, the manufacturingsequence useful for forming the multiple layers needed to fabricatedevice 60 and provide down-leads 701-706 (collectively 70) areemphasized. The further masking steps needed to laterally defineterminal connection pads 61, 65, capacitor 63 and inductor 64 will beunderstood by those of skill in the art and are omitted so that theprocess for forming down-leads 70 may be more easily understood. In step401 of FIG. 7, substrate 61 of, e.g., GaAs, and having upper surface 611is provided. In step 602 of FIG. 8, conductor layer 80 of, for example,TiWN or other materials that can provide electrical contact to substrate61 and of thickness in the range of usefully, at least 0.1K Angstromunits, conveniently 0.1K to 8K Angstrom units and preferably 2K to 4KAngstrom units is deposited. Chemical vapor deposition (CVD), plasmaenhanced chemical vapor deposition (PECVD), evaporation, sputteringand/or various combinations thereof are useful. Sputtering is preferred.In step 403 of FIG. 9, masking layer 82 (e.g., of photo-resist) isapplied and patterned to provide mask portions 821, 822 over conductorregions 801, 802 respectively where down-leads 70 are desired to contactsurface 611 of substrate 61. In step 404 of FIG. 10, those portions ofconductor 80 lying outside of masks 821, 822 are etched away, leavingbehind contact regions 801, 802 on surface 611 of substrate 61. FIGS.7-16, illustrate the case where only two down-leads 70 are beingprovided, wherein region 801 is intended to make contact to first metallayer 68 and region 802 is intended to make contact to second metallayer 69, however this is merely be by way of example and not intendedto be limiting. Persons of skill in the art will understand based on thedescription herein that any number of down-lead contacts may beprovided. In step 405 of FIG. 11, first dielectric layer 671 of, forexample, silicon nitride and of thickness in the range of usefully, atleast about 0.1K Angstrom units, conveniently 0.1K to 8K Angstrom unitsand preferably 1K to 2K Angstrom units is deposited over contact regions801, 802 and the remaining portions of surface 611 of substrate 61. Instep 406, FIG. 12, the result of applying a further masking layer (notshown) and etching opening 86 over contact region 801 in firstdielectric layer 671 is shown. Persons of skill in the art willunderstand how to perform such routine masking and etching steps. Instep 407 of FIG. 13, first metal layer of, for example, plated gold andof thickness in the range of, usefully, at least 1K Angstrom units,conveniently 1K to 120K Angstrom units and preferably 10K to 15KAngstrom units is deposited and patterned to provide lead 868 analogousto leads 701, 702 and 706 of FIG. 6 coupling first metal layer 68 tocontact region 801 on substrate 61. Lead 868 is conveniently a part offirst conductor layer 68. Only this small portion of first metal layer68 is shown in FIG. 13. First metal layer 68 extends laterally to suchregions as are needed to form the desired integrated passive device. Instep 408, FIG. 14, second dielectric layer 672 is provided of, forexample, silicon nitride, and of thickness in the range of usefully, atleast 0.1K Angstrom units, conveniently 0.1K to 8K Angstrom units andpreferably 2K to 3K Angstrom units is deposited, over first metal layer68 and the remaining portions of first dielectric layer 671, and thenpatterned in step 409 of FIG. 15 using means well known in the art, toprovide opening 89 over second contact region 802. In step 410, FIG. 16,second metal layer 69 is deposited over second dielectric layer 672 soas to fill opening 69 and provide conductor region 869 coupled tocontact region 802. Conductor region 869 in combination with contactregion 802 corresponds to down-leads 703-705 of device 60 of FIG. 6,that is, those down leads extending from second metal layer 69 tosubstrate 61. While second metal layer 69 is shown in FIG. 16 asextending everywhere, this is merely for convenience of explanation andpersons of skill in the art will understand that the lateral extent andshape of layer 69 is determined by the particular IPD being constructedand that it is appropriately masked and the unwanted regions removedusing means well known in the art. The purpose of FIGS. 7-16 is toillustrate how the various down-leads maybe formed coupling first metallayer 68 and/or second metal layer 69 to substrate 61. The lateraldefinition required to form terminal pads 62, 65, capacitor 63, inductor65 and/or any other desired components using metal layers 68, 69 anddielectric layers 671, 672 is understood by persons of ordinary skill inthe art.

FIGS. 17-24 are sequential cross-sectional views 401, 401-1, 401-2,401-2, 402-1, 403-1, 404-1 and 410-1 illustrated steps in a method offabrication of an integrated passive device analogous to sequence401-410 of FIGS. 7-16, but according to a yet further embodiment of thepresent invention. FIG. 25 is a plan view of a portion of the integratedpassive device illustrated in FIG. 23. Many of the steps in the methodof FIGS. 17-24 are similar to corresponding steps in the method of FIGS.7-16 and the convention is followed of designating analogous steps inthe method of FIGS. 17-24 by adding a suffix, e.g., step 403-1 isanalogous to step 403, step 404-1 is analogous to step 404, and soforth. The method of FIGS. 17-25 differ from the method of FIGS. 7-16 inthat an underlying high resistivity layer or region (e.g., region 901)is provided on upper surface 611 of substrate 61 for coupling thevarious down-leads 70 and is therefore suitable for use with insulatingsubstrates as well as semi-insulating substrates. Referring now to FIGS.17-24, in step 401, FIG. 17, substrate 61 with upper surface 611 isprovided. It is assumed for the purposes of this discussion thatsubstrate 61 is an insulating substrate. In step 401-1, layer 90 of highresistivity material is deposited on surface 611 of substrate 61. Highresistivity Si of thickness in the range of usefully at least 10Angstrom units (needs to be continuous), conveniently 100 to 5K Angstromunits and preferably 200 to 2K Angstrom units is deposited to form layer90. It is desirable that layer 90 have sheet resistances usefully in therange less than 1E11 Ohms per square, conveniently in the range of 1E6to 1E11 Ohms per square, and preferably in the range of 1E8 to 1E10Ohmsper square. While such sheet resistance values are useful, what isimportant is that the resistance of the charge bleed-off connection isat least 1E2 times and more preferably 1E3 to 1E4 times the impedance ofthe circuit being protected at the frequency range of interest. In step401-2, FIG. 19, mask region 92 of, for example, photoresist is providedhaving a lateral extent sufficient to couple the various down-leads 70that are needed for the integrated passive device being constructed. Instep 401-3, FIG. 20, the remainder of layer 90 is etched away so as toprovide desired high resistivity region 901 to which the variousdown-leads 70 can make contact. Steps 402-1, 403-1, and 404-1 of FIGS.21-23 are analogous to steps 402, 403, 404 of FIGS. 8-10 wherein contactlayer 80 is provided, masked by regions 821, 822 and etched to providedown-lead contact regions 801, 802, but which now rest on highresistivity region 902 rather than on surface 611 of substrate 61. Theremaining steps follow steps 405-410 of FIGS. 11-16, and result in thestructure shown in step 410-1 of FIG. 24. FIG. 25 shows a plan view ofregion 901 extending between down-leads 868 and 869. Persons of skill inthe art will understand that by varying the masking steps, region 901can be made to extend between any and all desired down-lead connections.Thus, the desired high resistivity coupling of the various elements ofIPD 40, 50, 60 can be made even on an insulating substrate. By providinginsulating or semi-insulating region 950 on or as a part of substrate 61(see FIGS. 17-24) beneath layer 92 and region 901, the present inventioncan be used with highly conductive substrates, since the desired highresistance connections between the various device elements can beprovided independent of the resistivity of substrate 61 below region950. Region 950 can be provided by depositing a layer of insulatingmaterial prior to step 401 and/or, depending upon the material chosenfor substrate 61, by doping the surface thereof to provide asubstantially intrinsic surface layer.

A number of integrated passive device RF couplers employing elementssuch as are illustrated in FIGS. 1-6, and incorporating the highresistance charge leakage paths described herein, were tested for ESDtolerance and compared with the results of testing an equal number ofotherwise substantially identical couplers without such high resistancecharge leakage paths. Signals corresponding to five human body model(HBM) positive pulses followed by five HBM negative pulses of increasingvoltage were applied and the onset of ESD damage determined. Forcouplers without the high resistance charge leakage connections of thepresent invention, the average ESD tolerance was about 525 volts. Forcouplers incorporating the high resistance charge leakage paths of thepresent invention described above, the average ESD tolerance was about950 volts for a structure where the high resistance charge leakage pathswere only coupled to the inductor, to about 969 volts for devices thatalso included such charge leakage paths coupled to the capacitor andterminal connection pads as well as the inductor. Thus, the means andmethod of the present invention provided a more than a 70% improvementin ESD performance for integrated passive devices without the need forany active devices being added to the circuits. While the presentinvention is particularly useful in connection with passive devices andhas been described herein by way of example for that situation, it isalso applicable to circuits containing active devices. For example, thehigh resistance charge leakage paths described herein can be applied tothe terminals of an integrated circuit or a transistor or a group oftransistors or bonding pads or other terminals coupled to active deviceswith beneficial results.

While various materials have been described for contact layer 80, firstdielectric layer 671, first metal layer 68, second dielectric layer 672and second metal layer 69, these are merely by way of example and notintended to be limiting. For example, the term “metal” as used herein isintended to include any form of sufficiently conductive material and notbe limited merely to simple metals and metal alloys. Non-limitingexamples of further useful materials are provided below:

Substrate:_InP, SiC, GaN, GaAs, Si, Glass, ceramic, plastic, plasticlaminate:

First dielectric layer: silicon nitride, silicon oxide, organicmaterials, glasses and other dielectrics:

First metal layer: Au, Ti, Pt, Cu, and mixtures and alloys thereof, TiW,TN, TiWN, WSi, and various other intermetallics and combinationsthereof:

Second dielectric layer: silicon nitride, silicon oxide, organicmaterials, glasses and other dielectrics:

Second metal layer: Au, Ti, Pt, Cu, and mixtures and alloys thereof,TiW, TN, TiWN, WSi, and various other intermetallics and combinationsthereof.

Such materials may be applied by various well known techniques such as,for example, and not intended to be limiting, CVD, PECVD, sputtering,evaporations, screen printing, plating and so forth.

According to a first embodiment, there is provided an integratedapparatus with ESD protection, comprising, one or more passive elementshaving portions potentially exposed to ESD transients, and one or morecharge leakage resistances extending between the portions potentiallyexposed to ESD transients, wherein the resistances have values muchlarger than the impedance of the one or more passive elements at theirnormal operating frequency. According to a further embodiment, the oneor more passive elements are formed on a semi-insulating substrate, andwherein the apparatus further comprises electrical leads coupling theportions potentially exposed to ESD transients to spaced-apart contactson the semi-insulating substrate, such that the charge leakageresistances are formed by the substrate resistance between thespaced-apart contacts. According to a still further embodiment, the oneor more passive elements are formed on an insulating substrate, and theapparatus further comprises, a high resistivity layer formed on thesubstrate beneath the one or more passive elements, and electrical leadscoupling the portions potentially exposed to ESD transients tospaced-apart contacts on the high resistivity layer such that the chargeleakage resistances are formed by the layer resistance between thespaced-apart contacts. According to a yet further embodiment, the one ormore passive elements are formed over a conductive substrate, and theapparatus further comprises, an insulating layer on the substrateelectrically isolating the elements from the substrate, a highresistivity layer formed on the insulating layer beneath the one or morepassive elements, and electrical leads coupling the portions potentiallyexposed to ESD transients to spaced-apart contacts on the highresistivity layer such that the charge leakage resistances are formed bythe layer resistance between the spaced-apart contacts. According to ayet still further embodiment, the charge leakage resistances are atleast about 100 times larger than the impedance of the apparatus at itsnormal operating frequency of interest. According to a still yet furtherembodiment, the apparatus further comprises an active device having atleast one terminal coupled to the one or more charge leakageresistances. According to another embodiment, the charge leakageresistances are at least about 500 times larger than the impedance ofthe apparatus at its normal operating frequency of interest. Accordingto a yet another embodiment, the charge leakage resistances are at leastabout 1000 times larger than the impedance of the apparatus at itsnormal operating frequency of interest.

According to a second embodiment, there is provided an ESD protectedintegrated electronic apparatus, comprising, an inductor, a capacitorcoupled to the inductor, two terminals coupled to the inductor and thecapacitor, and one or more charge leakage resistances coupled betweenthe two terminals. According to a further embodiment, the one or morecharge leakage resistances have values at least about 100 times largerthan the impedance of the apparatus as measured between the twoterminals at its normal operating frequency. According to a stillfurther embodiment, the one or more charge leakage resistances havevalues at least about 1000 times larger than the impedance of theapparatus as measured between the two terminals at its normal operatingfrequency. According to a yet further embodiment, at least one of theone or more charge leakage resistances is coupled to the inductor.According to a yet still further embodiment, at least one of the one ormore charge leakage resistances is coupled to the capacitor. Accordingto a still yet further embodiment, at least one of the one or morecharge leakage resistances is coupled between the two terminals.

According to a third embodiment, there is provided a method for formingan ESD protected electronic apparatus, comprising, providing asubstrate, forming at least two spaced-apart electrical contacts on thesubstrate, forming electric conductors extending from the at least twospaced-apart electrical contacts, and forming at least one passiveelement having portions in contact with the electric conductors.According to a further embodiment, the providing step comprisesproviding a substrate comprising a III-V material. According to a stillfurther embodiment, the III-V material comprises GaAs. According to ayet further embodiment, the step of forming the at least twospaced-apart electrical contacts on the substrate comprises, forming anelectrically insulating layer on or in an upper surface the substrate,forming a high resistivity layer on the insulating layer, and formingthe at least two spaced-apart contacts on the high resistivity layer.According to a yet still further embodiment, the step of formingelectrical conductors extending from the at least two spaced-apartelectrical contacts comprises, providing an electrically insulatinglayer over the at least two spaced-apart electrical contacts, patterningthe electrically insulating layer to expose at least a first of the atleast two spaced-apart electrical contacts, and applying a first metallayer over the first electrically insulating layer to form one of theelectric conductors in contact with the first of the at least twospaced-apart electrical contacts. According to a still yet furtherembodiment, the step of forming electrical conductors extending from theat least two spaced-apart electrical contacts further comprises, afterthe step of applying the first metal layer, applying a secondelectrically insulating layer over at least a portion the first metallayer, patterning the first and second electrical insulating layers toexpose a second of the at least two spaced-apart electrical contacts,and applying a second metal layer over the second electricallyinsulating layer to form a second electric conductor in contact with thesecond of the at least two spaced-apart electrical contacts.

While at least one exemplary embodiment has been presented in theforegoing detailed description, it should be appreciated that a vastnumber of variations exist. It should also be appreciated that theexemplary embodiment or exemplary embodiments are only examples, and arenot intended to limit the scope, applicability, or configuration of theinvention in any way. Rather, the foregoing detailed description willprovide those skilled in the art with a convenient road map forimplementing the exemplary embodiment or exemplary embodiments. Itshould be understood that various changes can be made in the functionand arrangement of elements without departing from the scope of theinvention as set forth in the appended claims and the legal equivalentsthereof.

1. A method for forming an electrostatic discharge (ESD) protectedelectronic apparatus, comprising: providing a substrate; forming adielectric layer over the substrate; forming a conductive layer over thedielectric layer; forming a first down-lead extending from theconductive layer, through the dielectric layer, and to the substrate;forming a second down-lead extending from the conductive layer, throughthe dielectric layer, and to the substrate, the second down-leadlaterally spaced apart from the first down-lead; and forming at leastone passive element electrically coupled to the first down-lead; whereinthe first down-lead, the second down-lead, and the substrate are formedsuch that a charge leakage resistance path is created between thefirst-down lead and the second down-lead through the substrate, thecharge leakage resistance path protecting the at least one passiveelement by inhibiting the accumulation of static charge during operationof the ESD protected electronic apparatus, the resistance between thefirst and second down-leads being at least 100 times an operatingimpedance of the ESD protected electronic apparatus.
 2. The method ofclaim 1, wherein the providing step comprises providing a substratecomprising a III-V material.
 3. The method of claim 2, wherein the III-Vmaterial comprises GaAs.
 4. The method of claim 1, wherein the providingstep comprises providing a substrate having a resistivity greater thanapproximately 1E3 ohms-cm.
 5. The method of claim 4, wherein theproviding step comprises providing a substrate having a resistivitybetween approximately 1E7 ohms-cm and approximately 1E9 ohms-cm.
 6. Amethod for forming an electrostatic discharge (ESD) protected electronicapparatus, the electronic apparatus configured to operate normally at apredetermined operating frequency, the method comprising: providing asubstrate; forming a dielectric layer over the substrate; forming aconductive layer over the dielectric layer; forming a first down-leadextending from the conductive layer, through the dielectric layer, andto the substrate; and forming a second down-lead extending from theconductive layer, through the dielectric layer, and to the substrate;and forming at least one passive element electrically coupled to thefirst down-lead; wherein the first down-lead, the second down-lead, andthe substrate are formed such that a high-resistance leakage path iscreated between the first and second down-leads through the substratethat inhibits the accumulation of static charge during operation of theESD protected electronic apparatus, and wherein the step of forming thefirst down-lead and the step of forming the second down-lead compriseforming the first and second down-leads such that the resistance betweenthe first and second down-leads is at least 100 times an operatingimpedance of the ESD protected electronic apparatus.
 7. The method ofclaim 6, wherein the step of forming the first down-lead and the step offorming the second down-lead comprise forming the first and seconddown-leads such that the resistance between the first and seconddown-leads is between approximately 1E6 ohms and approximately 1E11ohms.
 8. The method of claim 7, wherein the step of forming the firstdown-lead and the step of forming the second down-lead comprise formingthe first and second down-leads such that the resistance between thefirst and second down-leads is between approximately 1E8 ohms andapproximately 5E10 ohms.
 9. The method of claim 6, wherein the step offorming the first down-lead and the step of forming the second down-leadcomprise forming the first and second down-leads such that theresistance between the first and second down-leads is at least 1000times the operating impedance of the ESD protected electronic apparatus.